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| Datasheet File OCR Text: |
| september 2013 doc id 14219 rev 3 1/64 1 L9658 octal squib driver and quad sensor interface asic for safety application features 8 deployment drivers sized to deliver 1.2 a (min) for 2 ms (min) and 1.75 a (min) for 1 ms (min) independently controlled high-side and low- side mos for diagnosis analog output available for resistance squib short to ground, short to battery and mos diagnostic available on spi register capability to deploy th e squib with 1.2 a (min) or 1.75 a under 35 v load-dump condition and the low side mos is shorted to ground capability to deploy th e squib with 1.2 a (min) at 6.9 v vres and 1.75 a at 12 v vres interface with 4 satellite sensors programmable independent current trip points for each satellite channel support manchester pr otocol for satellite sensors supports for variable bit rate detection independent current limit and fault timer shutdown protection fo r each satellite output short to ground and short to battery detection and reporting for each satellite channel 5.5 mhz spi interface satellite message error detection hall effect sensor suppor t on satellite channels 3 and 4. low voltage internal reset 2 kv esd capability on all pins package: 64 leads lqfp technology: st proprietary bcd5s (0.57 m) description L9658 is intended to deploy up to 8 squibs and to interface up to 4 satellites . 2 satellite interfaces can be used to interface hall sensors. squib drivers are sized to deploy 1.2 a minimum for 2 ms minimum during load dump and 1.75 a minimum for 1ms minimum during load dump. diagnostic of squib driver and squib resistance measurement is controlled by micro controller. satellite interfaces supp ort manchester decoder with variable bit rate. lqfp64 table 1. device summary order code package packing L9658 lqfp64 tray L9658tr lqfp64 tape and reel www.st.com
contents L9658 2/64 doc id 14219 rev 3 contents 1 block diagram and application sc hematic . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 resetb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 msg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 deployment and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.1 chip select (cs_a, cs_d, cs_s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8.2 serial clock (sclk, sclk_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8.3 serial data output (miso, miso_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8.4 serial data input (mosi, mosi_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9.1 arming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10 depen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10.1 deployment driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.10.2 continuity diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10.3 short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 L9658 contents doc id 14219 rev 3 3/64 4.10.4 short to ground and open circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10.5 resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10.6 mos diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10.7 low side mos diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10.8 high side mos diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10.9 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.11 deployment driver spi bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.11.1 deployment driver mosi bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.11.2 deployment driver register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.11.3 deployment driver command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.11.4 deployment driver diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.11.5 example of short between loops diagnostic . . . . . . . . . . . . . . . . . . . . . 38 4.11.6 deployment driver monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.11.7 deployment driver miso bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.11.8 deployment driver register mode response . . . . . . . . . . . . . . . . . . . . . . 41 4.12 miso register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.12.1 deployment driver command mode response . . . . . . . . . . . . . . . . . . . . 43 4.12.2 deployment driver diagnostic mode response . . . . . . . . . . . . . . . . . . . . 44 4.12.3 deployment driver status response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.12.4 deployment driver spi fault response . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.13 arming spi bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.13.1 arming mosi_a bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.13.2 arm[01..67] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.13.3 arm[01..67]* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.13.4 arming miso_a bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.13.5 arm[01..67] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.14 satellite sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.14.1 current sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.14.2 manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.14.3 communication protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.14.4 "a" protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.14.5 "b" variable length protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.14.6 fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.14.7 satellite continuity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.14.8 (ifx/vx) hall effect support mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.14.9 (ifx/vx) raw data out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.14.10 message waiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 contents L9658 4/64 doc id 14219 rev 3 4.14.11 satellite serial data input (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.14.12 satellite mosi bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.14.13 satellite module configuration register ( ch1 only) . . . . . . . . . . . . . . . . 53 4.14.14 channel configurat ion registers (ccr1, ccr2, ccr3, ccr4) . . . . . . . 54 4.14.15 spi miso bits layout for configuration report . . . . . . . . . . . . . . . . . . . . 58 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 L9658 list of tables doc id 14219 rev 3 5/64 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. maximum operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. dc specification general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. dc specification: deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 8. satellite interface dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. ac specification: deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. ac specifications: satellite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. spi transmission during a deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. deployment driver spi response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. mosi bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. mosi mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. mosi register mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. pulse stretch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. mosi command mode message definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19. mosi diagnostic mode message definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 20. channel selection decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. mosi monitor mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 22. miso bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 23. miso mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. miso register mode response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 25. miso register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26. miso command mode response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. miso diagnostic mode response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 28. miso status response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 29. miso spi fault response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 30. arming mosi_a bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 31. arming miso_a bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 32. satellite mosi bits layo ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 33. mosi satellite interface registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 34. master configuration register definition (ch1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 35. channel configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 36. current ranges supported are given in following table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 37. satellite/deco der control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 38. "b" protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 39. bit time selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 40. mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 41. spi mode selects repl y for satellite channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 42. satellite miso bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 43. spi miso bits layout when reporting fifo data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 44. miso manchester message data definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 45. status bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 46. satellites fault codes definition supporting ?a? protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 47. satellites fault codes definition supporting ?b? protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 48. hall effect fault codes definition (ch3 and ch4) only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 49. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 list of figures L9658 6/64 doc id 14219 rev 3 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. mos settling time and turn-on time 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. mos settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. spi timing measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. spi block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. arming daisy-chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. arming spi transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. deployment sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. deployment flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. deployment driver diagnostic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 14. continuity diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. resistance measurement flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. low side diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. high side driver diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. satellite interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 19. manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 20. manchester dec oding using satellite protocol as an example . . . . . . . . . . . . . . . . . . . . . . 49 figure 21. "a" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. "b" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. lqfp64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 L9658 block diagram and application schematic doc id 14219 rev 3 7/64 1 block diagram and application schematic 1.1 block diagram figure 1. block diagram 1.2 application schematic figure 2. application schematic sensor interface deployment driver ich1 ich2 ich3 ich4 test reset msg vcc v8buck sqh0 sql0 sqh1 sql1 sqh2 sql2 sqh3 sql3 sqh4 sql4 sqh5 sql5 sqh6 sql6 sqh7 sql7 vres0 iref depen agnd dgnd cs_s sclk miso mosi cs_d gnd0 vres1 gnd1 vres2 gnd2 vres3 gnd3 vres4 gnd4 vres5 gnd5 vres6 gnd6 vres7 gnd7 aout cs_a sclk_a mosi_a spi arming interface if3/v3 if4/v4 miso_a cs_d cs_a miso mosi sclk cs_s miso_a mosi_a sclk_a depen aout gnd0 gnd7 gnd6 gnd5 gnd4 gnd3 gnd2 gnd1 gnd aout_gnd vres0 vres7 vres6 vres5 vres4 vres3 vres2 vres1 sqh0 sqh7 sqh6 sqh5 sqh4 sqh3 sqh2 sqh1 sql0 sql7 sql6 sql5 sql4 sql3 sql2 sql1 vdd ich4 ich3 ich2 ich1 resetb v8buck iref test 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.01f 0.01f 1000pf 1000pf 1000pf 1000pf 12.5k 0.01f vdd 0.01f 220f v8buck 220f 12.5k adc input processor i/o reset pin of power supply satellite sensor satellite sensor satellite sensor or hall effect switch satellite sensor or hall effect switch if4/v4 if3/v3 10nf 10nf vres 0.1f 3000f pin description L9658 8/64 doc id 14219 rev 3 2 pin description table 2. pin function pin # pin name description i/o type reset state 1 msg message waiting output pull-down 2 miso spi data out output hi-z 3 miso_a arming spi data out output hi-z 4 nc no connect - - 5 resetb reset pin input pull-up 6 gnd signal ground (analog & digital) - - 7 vdd vdd supply voltage input - 8 nc no connect - - 9 cs_a spi chip select for arming interface input pull-down 10 cs_s spi chip select for satellite interface input pull-down 11 cs_d spi chip select for deployment driver input pull-down 12 depen deployment enable input pull-down 13 mosi spi data in input hi-z 14 mosi_a arming spi data in input hi-z 15 sclk_a arming spi clock input hi-z 16 sclk spi clock input hi-z 17 gnd4 power ground for loop channel 4 - - 18 sql4 low side driver output for channel 4 output pull-down 19 sqh4 high side driver output for channel 4 output hi-z 20 vres4 reserve voltage for loop channel 4 input - 21 vres5 reserve voltage for loop channel 5 input - 22 sqh5 high side driver output for channel 5 output hi-z 23 sql5 low side driver output for channel 5 output pull-down 24 gnd5 power ground for loop channel 5 - - 25 gnd6 power ground for loop channel 6 - - 26 sql6 low side driver output for channel 6 output pull-down 27 sqh6 high side driver output for channel 6 output hi-z 28 vres6 reserve voltage for loop channel 6 input - 29 vres7 reserve voltage for loop channel 7 input - 30 sqh7 high side driver output for channel 7 output hi-z 31 sql7 low side driver output for channel 7 output pull-down 32 gnd7 power ground for loop channel 7 - - 33 nc no connect - - 34 if4/v4 current feedback for channel 4 raw or raw data output for channel 4 output hi-z 35 if3/v3 current feedback for channel 3 raw or data output for channel 3 output hi-z L9658 pin description doc id 14219 rev 3 9/64 2.1 thermal data 36 nc no connect - - 37 test test pin input pull-down 38 v8buck supply voltage for satellite interface and resistance measurement input - 39 nc no connect - - 40 ich4 current sense output for channel 4 output hi-z 41 ich3 current sense output for channel 3 output hi-z 42 ich2 current sense output for channel 2 output hi-z 43 ich1 current sense output for channel 1 output hi-z 44 nc no connect - - 45 iref external current reference resistor output - 46 aout_gnd ground reference for aout - - 47 aout analog output for loop diagnostics output hi-z 48 nc no connect - - 49 gnd3 power ground for loop channel 3 - - 50 sql3 low side driver output for channel 3 output pull-down 51 sqh3 high side driver output for channel 3 output hi-z 52 vres3 reserve voltage for loop channel 3 input - 53 vres2 reserve voltage for loop channel 2 input - 54 sqh2 high side driver output for channel 2 output hi-z 55 sql2 low side driver output for channel 2 output pull-down 56 gnd2 power ground for loop channel 2 - - 57 gnd1 power ground for loop channel 1 - - 58 sql1 low side driver output for channel 1 output pull-down 59 sqh1 high side driver output for channel 1 output hi-z 60 vres1 reserve voltage for loop channel 1 input - 61 vres0 reserve voltage for loop channel 0 input - 62 sqh0 high side driver output for channel 0 output hi-z 63 sql0 low side driver output for channel 0 output pull-down 64 gnd0 power ground for loop channel 0 - - table 2. pin function (continued) pin # pin name description i/o type reset state table 3. thermal data symbol parameter value. unit r th j-amb thermal resistance junction-to-ambient 68 c/w electrical specification L9658 10/64 doc id 14219 rev 3 3 electrical specification 3.1 maximum ratings the device may not operate properly if maximum operating condition is exceeded. 3.2 absolute maximum ratings caution: maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. table 4. maximum operating conditions symbol parameter value unit v dd supply voltage 4.9 to 5.1 v v 8buck v8buck voltage 7 to 8.5 v v res vres voltage (vres0, vres1 , vres2, vres3, vres4, vres5, vres6, vres7) 35 v v i discrete input voltage (resetb, depen, cs_a, cs_d, cs_s, sclk, sclk_a, mosi, mosi_a, miso, miso_a) -0.3 to (v dd +0.3) v t j junction temperature -40 to 150 c table 5. absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3 to 5.5 v v 8buck v8buck voltage -0.3 to 40 v v res vres voltage (vres0, vres1, vres2, vres3, vres4, vres5, vres6, vres7) -0.3 to 40 v sq l-h squib high and low side drivers (sqh0, sqh1, sqh2, sqh3, sqh4, sqh5, sqh6, sqh7, sql0, sql1, sql2, sql3, sql4, sq l5, sql6, sql7) -0.3 to 40 v v i discrete input voltage (resetb, depen, cs_a, cs_d, cs_s, sclk, sclk_a, mosi, mosi_a, miso, miso_a) -0.3 to 5.5 v ichx satellite input voltage (ich1, ich2, ich3, ich4) -3 to 40 v - analog/digital outputs voltage (aout, iref, msg, if3v3, if4v4) -0.3 to 5.5 v gndx ground pins voltage (gnd, aout_gnd, gnd0, gnd1, gnd2, gnd3, gnd4, gnd5, gnd6, gnd7) -0.3 to 5.5 v t j maximum steady-state junction temperature 150 c t amb ambient temperature -40 to 95 c t stg storage temperature -65 to 150 c L9658 electrical specification doc id 14219 rev 3 11/64 3.3 electrical characteristics 3.3.1 dc characteristics v res = 6.5 to 35 v, v dd = 4.9 to 5.1 v, v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c table 6. dc specification general symbol parameter test condition min. typ max. unit v rst (1) internal voltage reset v dd v dd drops until deployment drivers are disabled 4.0 - 4.5 v v rst_l (2) 2.1 - 3.0 i dd input current v dd normal operation; i ch1-4 = 0 a 6.2 - 8.6 ma short to ?0.3 v on sqh; i ch1-4 = 0 a 5.5 - 9.5 short to ?0.3 v on sql; i ch1-4 = 0a 5.5 - 9.5 deployment; i ch1-4 = 0 a 5.5 - 9.5 r iref_h resistance threshold i ref - 20.0 - 60.0 k ? r iref_l - 2.0 - 9.0 k ? v ih_resetb input voltage threshold resetb ---2.0v v il_resetb -0.8--v v hys -100-400mv v ih_depen input voltage threshold depen --2.0v v il_depen -0.8--v i pd input pull-down current depen v in = v il to v dd 10 - 50 ? a v ih_test input voltage threshold test ---3.6v v il_test -0.8--v i test input pull-down current test test = 5 v 1.0 - 2.5 ma i pu input pull-up current resetb resetb = v ih to gnd 10 - 60 ? a i v8buck current consumption v8buck -25-40a v ih input voltage threshold mosi, mosi_a, sclk, sclk_a, cs_s, cs_d, cs_a input logic = 1 - - 2.0 v v il input logic = 0 0.8 - - v v hys -100-400mv i lkg input leakage current mosi, mosi_a, sclk, sclk_a v in = v dd --1 ? a v in = 0 to v ih -1 - - ? a i pd input pull-down current cs_s, cs_d, cs_a v in = v il to v dd 10 - 50 ? a v oh output voltage miso, miso_a, msg i oh = -800 ? av dd ?0.8 - v v ol i ol = 1.6 ma - - 0.4 v i hi_z tri-state current miso, miso_a, miso = vdd - - 1 ? a miso = 0 v -1 - - ? a 1. v rst shall have a por de-glitch timer. 2. v rst l shall have no timer. electrical specification L9658 12/64 doc id 14219 rev 3 v res = 6.5 to 35 v, v dd = 4.9 to 5.1 v, v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c table 7. dc specification: deployment drivers symbol parameter test conditions min. typ max. units v oh output voltage aout high saturation voltage; i aout = -500 ? a v dd - 0.4 --v v ol low saturation voltage; i aout = +500 ? a --0.3v i z tri-state current aout aout = v dd --1 ? a aout = 0 v -1 - - ? a i lkg leakage current sqh v8buck = v dd = 0, v res = 36 v, v sqh = 0v --50 ? a i stg v8buck = 18 v; v dd = 5 v; v sqh = -0.3 v -5 - - ma i lkg bias current vres (1) v8buck = 18 v; v dd = 5 v; v res = 36 v; sqh shorted to sql --10 ? a i lkg leakage current sql v8buck = v dd = 0, v sql = 18 v -10 - 10 ? a i stg v8buck = 18 v; v dd = 5 v; v sql = -0.3 v -5 - ma i stb v8buck = 18 v; v dd = 5 v; v sql = 18 v -5ma i pd pull-down current sql v sql = 1.8 v to v dd 900 - 1300 ? a i pd_sqh pull-down current sqh v sqh = sbth to v res 900 - 1300 ? a v bias diagnostics bias voltage i sqh = -1.5 ma (nominal: 2.0 v) 1.80 - 2.20 v i bias diagnostics bias current v sqh = 0 v -7 - i pd v stb short to battery threshold (nominal 3.0 v) 2.70 - 3.30 v v stg short to ground threshold (nominal 1.0 v) 0.90 - 1.10 v v i_th mos test load voltage detection - 100 - 300 mv i src resistance measurement current source v dd = 5.0 v; v8buck = 7.0 v to 26.5 v 38 - 42 ma i sink resistance measurement current sink -45-55ma r dson total high and low side mos on resistance high side mos + low side mos v res = 6.9 v; i = 1.2 a @95 c --2.0 ? r dson high side mos on resistance v res = 35v; i vres = 1.2a; t amb = 95c - - 0.8 ? r dson low side mos on resistance v res = 35v; i vres = 1.2a; t amb = 95c - - 1.2 ? i depl_12a deployment current mosi register mode bit d10=?0? r load = 1.7 ???? v res = 6.9 to 35 v 1.20 - 1.47 a i depl_175a mosi register mode bit d10=?1? r load = 1.7 ???? v res = 12 to 35 v 1.75 - 2.14 a i lim low side mos current limi tr load = 1.7 ? 2.15 - 3.5 a r l range load resistance range (2) - 0 - 10.0 ? 1. not applicable during a diagnostic. 2. test conditions for load resistance measurements L9658 electrical specification doc id 14219 rev 3 13/64 v dd = 4.9 to 5.1v , v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c table 8. satellite interface dc specifications symbol parameter test conditions min typ max unit i_lim current limit high side short to -0.3 v (-)75 - (-)150 ma high side short to battery - - 5 ma v8buck =vcc=0 measured @ v8buck ---1ma vhdp high side voltage drop i=50 ma @105 c; v8buck=7.0 v --1v i=25 ma @105 c; v8buck=7.0 v --0.5v ifr if/iout ch3 & ch4 iout = -50ma 460 - 540 ? a iout = -5ma 46 - 54 ? a itr low to high transition current threshold spi channel configuration bit <2:0 ? 111 54.00 - 66.00 ma bit <2:0 ? 110 43.65 - 53.35 ma bit <2:0 ? 101 35.10 - 42.90 ma bit <2:0 ? 100 28.80 - 34.20 ma bit <2:0 ? 011 24.85 - 29.15 ma bit <2:0 ? 010 20.25 - 24.75 ma bit <2:0 ? 001 17.10 - 20.90 ma bit <2:0 ? 000 14.85 - 18.15 ma v clamp if/vx ch3 & ch4 clamp voltage rext=33.3 k ? ; chx is shorted to gnd 0.95* vdd - 1.05* vdd v ihyst current threshold hysteresis sink current = ithr at the output (ichx). ihyst=trip point high ? trip point low 0.05*itr - 0.15*itr ma vos short to bat feedback current v(ichx)-v8buck<50mv - - 25 ma olkg output leakage current ich x v=18 v @ pin under test - - 1 ? a electrical specification L9658 14/64 doc id 14219 rev 3 3.3.2 ac characteristics v res = 6.5 to 35 v, v dd = 4.9 to 5.1 v, v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c table 9. ac specification: deployment drivers symbol parameter test co nditions min typ max unit t por por de-glitch timer timer for v rst 10 - 25 ? s t glitch de-glitch timer - 5 - 20 ? s i on diagnostic current depen pins asserted; measured at 150 ? s from falling edge cs_d or cs_a; see figure 4 0.90 - - i final t pulse pulse stretch timer see ta bl e 1 7 0-60ms t p_acc pulse stretch timer accuracy - -20 - 20 % t deploy-2ms deployment time v res = 6.9 to 35 v (1) 2-2.5ms t deploy-1ms deployment time v res = 12 to 40 v (1) 1 - 1.15 ms t flt_dly fault detection filter (2) -10-50 ? s i slew rmeas current di/dt 10 % - 90 % of i src 2-8 t r_dly rmeas current delay from the falling edge of cs to 10 % of i src --15 ? s t r_wait rmeas wait time (2) wait time before aout voltage is stable for adc reading - - 100 ? s t timeout mos diagnostic on-time - - - 2.5 ms t ilim sql high current protection timer - 90 - 110 ? s t prop_dly ls/hs mos turn off propagation delay (2) time is measured from the valid ls/hs mos fault to the ls/hs turn off --10 ? s 1. application information; test is not performed at high voltage. 2. design information only ma ? s -------- - L9658 electrical specification doc id 14219 rev 3 15/64 figure 3. mos settling time and turn-on time 1 figure 4. mos settling time and turn-on time 2 i final 110% i final 90% i final t settle i peak t on i peak = i final 110% i final 90% i final t settle = t on electrical specification L9658 16/64 doc id 14219 rev 3 v dd = 4.9 to 5.1 v ; v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c table 10. ac specifications: satellite symbol parameter test co nditions min typ max unit osc internal oscillator frequency tested with 12.5k 1% iref resistor 4.45 5.55 mhz mdf de-glitch filter as a function of protocol speed manchester protocol excluding osc tolerance bit<8:7 ? 00 bit<8:7 ? 01 bit<8:7 ? 10 bit<8:7 ? 11 11.76 %*bit- time - 23.53 % *bit- time ? s bitr minimum frequency operating range (incoming messages fall within this operating range is guaranteed to be accepted by the ic) channel configurations bit<8:7 ? 00 test at frq = 52.33 khz test at frq =13.32 khz 13.32 - 52.33 khz bit<8:7 ? 01 test at frq =110.74 khz test at frq = 26.32 khz 26.32 - 110.74 khz bit<8:7 ? 10 test at frq =164.20 khz test at frq = 43.50 khz 43.50 - 164.20 khz bit<8:7 ? 11 test at frq =250.63 khz test at frq = 62.66 khz 62.66 - 250.63 khz bitr maximum frequency operating range (incoming messages fall outside this operating range is guaranteed to be rejected by the ic) channel configurations bit<8:7 ? 00 test at frq > 59.14 khz test at frq <11.99 khz 11.99 - 59.14 khz bit<8:7 ? 01 test at frq>128.37 khz test at frq <23.57 khz 23.57 - 128.37 khz bit<8:7 ? 10 test at frq>194.93 khz test at frq <38.71 khz 38.71 - 194.93 khz bit<8:7 ? 11 test at frq>309.6 khz test at frq <55.37 khz 55.37 - 309.6 khz idle idle time manchester 2 - - bit times tdl & tdh ifx/vx delay test with12.5k 1% iref resistor check response from changing between the following current levels. high =0-15 ma, low = 66 to 150 ma -1- ? s tdl - tdh ifx/vx delay time differential ich x outputs with a 500 ? s symmetrical pulse in and 500 ? s out. --0.3 ? s flt output fault timer i_sensor > i_lim 300 - 500 ? s L9658 electrical specification doc id 14219 rev 3 17/64 v res = 6.5 to 35 v, v dd = 4.9 to 5.1 v. v 8buck = 7.0 v to 8.5 v, t amb = -40 c to +95 c all spi timing is performed with a 200 pf load on miso unless otherwise noted. figure 5. spi timing diagram figure 6. spi timing measurement table 11. spi timing no. symbol parameter min typ max unit - fop transfer frequency dc - 5.50 mhz 1t sck sclk, sclk_a period 181 - - ns 2t lead enable lead time 65 - - ns 3t lag enable lag time 50 - - ns 4t sclkhs sclk, sclk_a high time 65 - - ns 5t sclkls sclk, sclk_a low time 65 - - ns 6t sus mosi, mosi_a input setup time 20 - - ns 7t hs mosi, mosi_a input hold time 20 - - ns 8t a miso, miso_a access time - - 60 ns 9t dis miso, miso_a disable time (1) --100ns 10 t vs miso, miso_a output valid time - - 66 ns 11 t ho miso, miso_a output hold time (1) 0- -ns 12 t ro rise time (design information) - - 30 ns 13 t fo fall time (design information) - - 30 ns 14 t csn cs_a, cs_d, cs_s negated time 640 - - ns 1. parameters t dis and t ho shall be measured with no addit ional capacitive load beyond the nor mal test fixture capacitance on the miso pin. additional capac itance during the disable time test erroneously extends the m easured output disable time, and minimum capacitance on miso is the worst case for output hold time. sclk don't care miso mosi cs t lag t csn f op t sclkhs t lead t sclkls t vs t a t sus t hs t ro , t fo t ho t dis msb in lsb in data msb out lsb out data +5 v 1.0 v 4.0 v 0v cs miso vdd miso t dis 1k 1k functional description L9658 18/64 doc id 14219 rev 3 4 functional description 4.1 overview L9658 is an integrated circuit to be used in air bag systems. its main functions include deployment of air bags, switch ed-power sources to satellite sensors, diagnostics of sdm (sensing deployment module) and arming inputs. L9658 supports 8 deployment loops, 4 satellite-sensor in terfaces, and spi arming inputs. 4.2 power on reset (por) L9658 has a power on reset (por) circuit, which monitors v dd voltage. when v dd voltage falls below v rst for longer than or equal to t por , all outputs are disabled and all internal registers are reset to their default condition. when v dd falls below v rst_l , all outputs are disabled and all internal registers are reset to their default condition. no delay filter shall be used along with v rst_l threshold. if v dd voltage falls below v rst for less than t por , operation shall not be interrupted. when v dd rises above v rst , the outputs are enabled. before v dd reaches v rst , and during t por , none of the outputs turn on. 4.3 resetb resetb pin is active low. the effects of r esetb are similar to those of a por event, except during a deployment. when L9658 has a deployment in-progress, it ignores resetb signal. however, it shall shut itself down as soon as it detects a por condition. when the deployment is completed and r esetb signal is asserted, the device disables its outputs and reset its internal registers to their default states. a de-glitch timer is provided to resetb pin. the timer protects this pin against spurious glitches. ut48 neglects resetb signal if it is asserted for shorter than t glitch . resetb has an internal pull-up in case of an open circuit. this pin has a de-glitch timer 4.4 msg msg pin is used to reflect fifo status. its polarity can be configured and also the strategy of activation. polling mode: message pin shall be active as soon as one of the 4 fifo will be not empty and it will be inactive when al l 4 fifo will be empty. a micr ocontroller can periodically monitor the status of line to understand ther e are data received from satellite. interrupt mode: message pin shall be acti ve as soon one of the 4 fifo will be not empty and it will be inactive when a spi communication on cs_s interface starts. at the end of the spi communication it shall be active if one of the 4 fifo will be not empty. otherwise shall be kept inactive. a microcontroller can wait until an edge is present on the line and manage the data available in the fifo. L9658 functional description doc id 14219 rev 3 19/64 4.5 iref i ref pin shall be connected to v dd supply through a resistor, r iref . when the device detects the resistor on i ref pin is larger than r iref_h or smaller than r iref_ l, it goes in reset condition. all outputs are disabled and all internal registers are reset to their default conditions. 4.6 loss of ground when gnd pin is disconnected from pc-board ground, L9658 goes in reset condition. all outputs are disabled and all internal registers are reset to their default conditions. a loss of power-ground (gnd0 ? gnd7) pin/s disables the respective channel/s. in other words, the channel that loses its power gr ound connection will not be able to deploy. the rest of the device is not affected by a loss of power-ground condition. a out_gnd pin is a reference for a out pin. when aout_gnd loses its connection the reset as well. 4.7 deployment and reset the following conditions reset and terminate deployments: power on reset (por) iref resistance is larger than r iref_h or smaller than r iref_l loss of ground condition on gnd pin the following conditions are ignored when it has a deployment in-progress: resetb valid soft reset sequences 4.8 serial peripheral interface (spi) the device contains a serial peripheral in terface consisting of serial clock (sclk, sclk_a), serial data out (miso, miso_a), serial data in (mosi, mosi_a), and two chip selects (cs_a, cs_d and cs_s). this device is configured as an spi slave. the idle state of the communication, serial clock (sclk, sclk_a) should be low state. functional description L9658 20/64 doc id 14219 rev 3 figure 7. spi block diagram L9658 has a counter to verify the number of clocks in sclk and sclk_a. if the number of clocks in sclk is not equal to 16 clocks while cs_d is asserted, it ignores the spi message and send a spi fault response. if the number of clocks in sclk is not equal to 64 clocks while cs_s is asserted, it ignores the entire spi message and push the bad spi bit count fault code into the fifo. if the number of clocks in sclk_a is not a multiple of 8, it ignores the command in the arming shift register. otherwise, the device latch-in the command. figure 8. arming daisy-chain configuration arming spi interface is based on 8-bit data transfer. the device is capable to receive a multiple of 8-bit command s. the first byte of data coming out of miso_a will be the arming status bits. the subseq uent bits will be the arming comman d bits received through mosi_a pin. refer to below figure for an example of arming spi transmission. this is an example of arming spi transmission based on the daisy-chain configuration. in case of daisy chain connection for arming spi, device works as following: all devices ic_1, ic_2, ic_3 shi fted out data on the falling edge of sclk_a for the first 8 bits and shifted out data on the rising edge of sclk_a for the bits after 8bits. therefore p, ic_3, ic_2 shall strobe 24bits on rising edge of sclk_a, the first 8 bits are produced (by ic_3, ic_2, ic_1 respectively) on the falling edge of sc lk_a. the remaining 16 bits are shifted out on the rising edge. miso msb lsb control bits status bits input shift register sclk mosi cs_d output shift register cs vdd vss 30a cs_s 30a miso_a msb lsb control bits status bits sclk_a mosi_a cs_a shift register cs vdd vss 30a miso mosi cs sclk mosi_a miso_a cs_a sclk_a ic_1 ic_3 ic_2 p mosi_a miso_a cs_a sclk_a cs_a sclk_a mosi_a miso_a L9658 functional description doc id 14219 rev 3 21/64 figure 9. arming spi transmission 4.8.1 chip select (cs_a, cs_d, cs_s) chip-select inputs select L9658 for serial transfers. cs_a is independent to cs_d and cs_s. cs_a can be asserted regardless of cs_d and cs_s. however, either cs_d or cs_s can be asserted at any given time. if both cs_d and cs_s inputs are selected simultaneously, the device ignores mosi command. when ch ip-select is asserted, the respective miso/miso_a pin is released from tri-state mode, and all status information is latched in the spi shift register. while chip-select is asserted, register data is shifted into mosi/mosi_a pin and shifted out of miso/miso_a pin on each subsequent sclk/sclk_a. when chip-select is negated, miso/miso_a pin is tri-stated. to allow sufficient time to reload the registers; chip-select pin shall remain negated for at least tcsn. chip-select is also immune to spurious pulses of 50 ns or shorter (miso/miso_a may come out of tri-state, but no status bits is cleared and no control bits is changed). chip-select inputs have current sinks on the pins, which pull these pins to the negated state when an open circuit condition occur. these pins have ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 v supply. 4.8.2 serial clock (sclk, sclk_a) sclk/sclk_a input is the clock signal input for synchronization of serial data transfer. this pin has ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 v supply. when chip select is asserted, both the spi master and this device shall latch input data on the rising edge of sclk/sclk_a. L9658 shift data out on the falling edge of sclk/sclk_a. the sclk/sclk_a must be taken in idle state (low) when the cs_a,cs_d,cs_s ar e in idle state (low). (a) 4.8.3 serial data outp ut (miso, miso_a) miso/miso_a output pin shall be in a tri-state condition when chip select is negated. when chip select is asserted, the msb is the first bit of the word/byte transmitted on miso/miso_a and the lsb is the last bit of the word/byte transmitted. this pin supplies a rail to rail output, so if interfaced to a microprocessor that is using a lower vdd supply, the appropriate microprocessor input pin shall not sink more than ioh (min) and shall not clamp the miso/miso_a output voltage to less than voh (min) while miso/miso_a pin is in a logic ?1? state. ic_1 miso_a, ic_2 mosi_a p mosi, ic_1 mosi_a p cs, ic cs_a ic_3 miso_a, p mosi ic_2 miso_a, ic_3 mosi_a command #1 command #2 command #3 ic_1 status command #1 command #2 ic_2 status ic_1 status command #1 ic_3 status msb lsb ic_2 status ic_1 status a. only in daisy chain, it is needed to guarantee on sclk _a a clock skew of 3ns maximum between any devices. functional description L9658 22/64 doc id 14219 rev 3 4.8.4 serial data i nput (mosi, mosi_a) mosi/mosi_a input takes data from the master processor while chip select is asserted. the msb shall be the first bit of each word/byte received on mosi/mosi_a and the lsb shall be the last bit of each word/byte rece ived. this pin has ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 v supply. 4.9 deployment drivers the on-chip deployment drivers are designed to deliver 1.2 a (min) at 6.9 v vres. deployment current is be 1.2 a (min) for 2 ms (min). the high side driver survives deployment with 1.47 a, 35 v at vres and sql is shorted to ground for 2.5ms. minimum load resistance is 1.7. at the end of a deployme nt, a deploy success flag is asserted via spi. each vres and gnd connection are used to accommodate 8 loops that can be deployed simultaneously. upon receiving a valid deployment condition, the respective sqh and sql drivers are turned on. sqh and sql drivers are also turned on momentarily during a mos diagnostic. otherwise, sqh and sql are inactive under any normal, fault, or transient conditions. upon a successful deployment of the respective sqh and sql drivers, a deploy command success flag is asserted via spi. refer to " deployment sequence" figure for the valid condition and the deploy success flagh timing. figure 10. deployment drivers diagram iref depen vbuck8 spi sqh0 sql0 vres0 sqh1 sql1 sqh5 sql5 sqh4 sql4 vres4 sqh2 sql2 l s d h s d isense isense diagnostic sqh3 sql3 l s d h s d isense isense diagnostic sqh7 sql7 l s d h s d isense isense diagnostic sqh6 sql6 l s d h s d isense isense arm45 diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic gnd0 gnd4 arm01 arm23 arm45 arm67 logic arm67 arm01 arm23 por vres2 test vres3 vres6 vres7 gnd2 gnd3 gnd6 gnd7 gnd1 gnd5 vres1 vres5 aout L9658 functional description doc id 14219 rev 3 23/64 the following power-up conditions is considered as normal operations. vres input can be connected to either a power supply output or an ignition voltage. vdd is connected to 5 v output of power supply. when vres is conne cted to the power supply, vdd voltage will reach its regulation volt age before vres voltage is stabilized. in this condit ion, the device has the control o f its internal logic and that prevent an inadvertent turn-on of the drivers. when vres is connected to the ignition, vres voltage will be stabilized before vdd reaches its regulation voltage. in this conditi on, all drivers are inactive. a pull-down on the gates of high side drivers (sqh) is provided to prevent these drivers from momentarily turning-on. any loop driver fault conditions do not turn on the sqh and sql drivers. only a valid deployment condition can turn on the respective sqh and sql drivers. refer to section for valid deployment conditions. 4.9.1 arming interface the arming interface is used as a fail-safe to prevent inadvertent airbag deployment. along with deployment command, these signals provide redundancy. pulse stretch timer is provided for each channel/loop. either arm signal or deployment command shall start the pulse stretch timer. arming interface has a dedicated 8-bit spi interface. when cs_a is negated, L9658 latch arm signal from the shift register and start the pulse stretch timer for the respective channel/s. the device can deploy a channel, only when depen is asserted and any of the following conditions are satisfied: ? the respective deployment command is sent during a valid pulse stretch timer, which initiated by arm signal ? the respective spi arm command is sent during a valid pulse stretch timer, which initiate by deployment command during a deployment, the device turn on the respective high side (sqh) and low side (sql) drivers for duration of t deploy . when a deployment is initiated, it cant be terminated, except during a reset event. figure 11. deployment sequence when a deployment-enable command is sent through spi, the pulse stretcher shall be initiated immediately following the falling edge of cs_d. when another depl oyment-enable pulse stretch timer t deploy deploy valid deployment window cs _d deploy success flag 1: deployment-enable command 2: clear deploy success flag spi cs_d notes: 112 t pulse valid deployment window 11 2 valid deployment window t < t pulse valid deployment window t L9658 functional description doc id 14219 rev 3 25/64 during the deployment, L9658 turn on the respective high (sqh) and low side (sql) drivers for tdeploy. once deployment is initiated it can not be terminated. when a channel is in deployment, this particular channel shall only act upon certain spi messages. these spi messages and their responses are summarized in below table. the rest of the channels shall resume their operations and respond to specific spi commands. during a deployment, the device ignores arming commands. and does not refresh or terminate the pulse stretch timer when it receives an arming command. 4.10 depen depen is a deployment enable input, which is an active high input. when this pin is asserted, L9658 is able to turn on its high and low side drivers upon receiving a valid deployment command or a mos diagnostic requ est. depen can not in terrupt a deployment that is already in-progress. when depen is negated, it inhibits the low side and the high side mos from turning on (inhibit the deployment). when a mos diagnostic is requested, the device executes the diagnostic even without the ability to turn on th e mos. it set the prop er spi threshold bits. spi remains functional while this pin is pulled low. when depen is negated, spi deploy command is prevented from initia ting the pulse stretch timer. regardless of depen, spi deploy command status bits reports the state of spi deploy command bits sent in the previous spi transfer. this feature is required so that the processor can diagnose spi deploy command bits with depen negated. regardless of depen, arming signal is able to initiate the pulse stretc h timer. this feature will be used for the processor to diagnose the arming signal. when the pulse stretch timer has been running, changes in the state of depen does not affect the pulse stretch timer. the pulse stretch timer is not affected regardless of the pulse stretch timer being started by an arming signal or a spi deploy command. a de-glitch timer is provided to depen pin. the timer protects this pin against spurious glitches. the device neglects depen signal if it is asse rted/negated for shorter than t glitch . table 12. spi transmission during a deployment spi mosi spi miso (1) 1. spi miso sent in the next spi transmission. notes register mode spi fault response mosi register mode message shall be ignored command mode command mode execute for channels not in deployment; no effect to deploying channel diagnostic mode spi fault response mosi diagnostic mode message shall be ignored monitor mode status response execute for all channels functional description L9658 26/64 doc id 14219 rev 3 4.10.1 deployment driver diagnostic L9658 is able to perform a short to battery, a short to ground, a resistance measurement and a mos diagnostics on its deployment drivers. a short to ground and an open circuit conditions are distinguished using a resistance measurement. here below is shown the diagram of deployment driver diagnostic. the diagnostic is performed when a valid spi command is received. each current sources (i src and i bias ) and current sinks (i sink , i pd_sqh ) are turn on or off by a spi command. i pd_sqh is turned on when i bias is turned on. this pull-down (i pd_sqh ) is used to deplete the charge left on the sqh and sql capacitors. ipd is permanently connected to sql. this current sink pull-down sql pin during an open circuit condition. diagnostic current source or sink and comparator or amplifier are independent. it is possible to turn on or off the current source or sink on a specific channel, while monitoring the comparator or amplifier on a different channel. this feature is used to run a short between loop diagnostic. figure 13. deployment driver diagnostic diagram diagnostic logic amux spi sclk cs miso mosi sqlx over-current detection sqhx i src v8buck vresx i bias v bias amp resistance measurement cmp1 aout gate drive v i_th sbth sgth i sink i pd gndx i pd_sqh ac00211 L9658 functional description doc id 14219 rev 3 27/64 4.10.2 continuity diagnostic a continuity diagnostic includes a short to ba ttery, a short to ground and an open circuit diagnostics. during a continuity diagnostic, ibias is switched on. on a normal loading condition, sqh voltage is below sbth threshold and sq l voltage will be above sgth threshold. figure 14. continuity diagnostic flow chart 4.10.3 short to battery a short to battery condition will be detected w hen the voltage on sqh is greater than sbth threshold voltage. 4.10.4 short to ground and open circuit a short to ground or an open circuit conditions are detected when the voltage on sql is less than sgth threshold voltage. a resistance me asurement is utilized to differentiate between a short to ground or an open circuit conditions. begin sqh > sb th during t flt_dly end spi command: connect i bias sql < sg th during t flt_dly clear sbth and sgth bits disconnect i bias y spi response: send sbth and sgth bits set spi.diag.sb th set spi.diag.sg th spi command: disconnect i bias n y t flt_dly = 20 s n note: spi transmission and spi command can be sent in the same cs_d. spi transmission y y clear spi.diag.sg th clear spi.diag.sb th n sqh < sb th during t flt_dly n sql > sg th during t flt_dly y y n functional description L9658 28/64 doc id 14219 rev 3 4.10.5 resistance measurement during a resistance measurement, both isrc and isink are switched on. an analog voltage on a out pin is provided. a out pin is a 5 v analog pin, which will be connected to the adc input of a processor. this pin provides the resistance-measurement voltage, which correspond to the voltage difference across sqh and sql. according to the following formula: v aout = v dd /10 + r squib i src 10 the accuracy in the range of r squib is classified as followings: 0 < r squib ? 3.5 ? 95 mv 3.5 < r squib ? 10 ? 5 % a low pass filter (10 k ? + 330 pf) is recommended in order to cancel noise caused by internal offset compensation. figure 15. resistance measurement flow chart 4.10.6 mos diagnostics during diagnostic, ibias is connected to sqh pin. in a normal condition, sqh voltage is below sb th and sql voltage will be higher than sg th. prior to turning on the mos, the processor is expected to check for a short to battery and a short to ground fault. this step is intended to prevent a large amount of current flowing through the mos. also, this step is intended to precondit ion sqh and sql pins prior to diagno stics. depen pin is asserted in order to turn on the low or high side driver . if depen is negated du ring diagnostic, the mos is not turned on and a fail mos diagnostic is expected. 4.10.7 low side mos diagnostic when L9658 receives a spi command to initiate the low side driver diagnostic, verification of following conditions are done before turning on the low side driver: ?v sql greater than sg th threshold voltage ?v sqh less than sbt h threshold voltage if both conditions above are satisfied, execution of low side driver diagnostic is performed. otherwise, the low side mos diagnostic request is ignored and both bit d13 and bit d7 in spi diagnostic mode response are set. upon detection of the following conditions, the begin end spi command: enable aout, turn on i src & i sink spi command: turn off i src & i sink turn off i src & i sink y n L9658 functional description doc id 14219 rev 3 29/64 device turns the low side driver off and terminate the diagnostic within the specified time, t prop_dly . ?v sql less than sg th threshold voltage ?(v sqhx ? v sqlx ) greater than v i_th ?v sqh greater than sb th threshold voltage the state of each comparator above is reported through spi. when the device detects one of the above conditions, the respective spi status bit to indicate the condition is set. any of the above conditions will be considered as normal in a low side mos diagnostic. the low side driver is turned off when t timeout is expired. a fault detection filter, t flt_dly , is provided to protect against short-transients on sqh and sql pins. figure 16. low side diagnostic flow chart y n t timeout = 2ms spi command: disconnect i bias y n spi command: ls fet test t flt_dly = 20 s note: spi transmission and spi command can be sent in the same cs_d. turn on ls fet end switch off ls fet disconnect i bias y spi transmission clear v i_th , sb th , and sg th bits spi response: send v i_th , sb th and sg th bits spi command: disconnect i bias y n n (sqh-sql) > v i_th or sqh > sb th during t flt_dly y n sql < sg th during t flt_dly y n set spi.diag.sg th set spi.diag.v i_th or set spi.diag.sb th t > t timeout n y sqh < sb th and sql > sg th y n set spi.diag.sb th and set spi.diag.sg th y n spi command: d6..d4 == d2..d0 set spi.diag.sb th and set spi.diag.sg th and set spi.diag.v i_th spi command diag mode d11=0 or cmd mode message y n begin sqh > sb th during t flt_dly spi command: connect i bias sql < sg th during t flt_dly clear sbth and sgth bits y spi response: send sbth and sgth bits set spi.diag.sb th set spi.diag.sg th n spi transmission y y clear spi.diag.sg th clear spi.diag.sb th n sqh < sb th during t flt_dly n sql > sg th during t flt_dly y y n functional description L9658 30/64 doc id 14219 rev 3 4.10.8 high side mos diagnostic when L9658 receives a spi command to initiate the high side mos diagnostic, the following conditions are verified before turning on the high side mos: ?v sql greater than sg th threshold voltage ?v sqh less than sb th threshold voltage if both conditions above are satisfied, the high side mos diagnostic is executed. otherwise, it ignored and both bit d13 and bit d7 in spi diagnostic are set. upon detection of the following conditions, the high side driver is turned off and the diagnostic, within the specified time, t prop_dly , is terminated ?v sqh greater than sb th threshold voltage ?(v sqhx ? v sqlx ) greater than v i_th ?v sql less than sg th threshold voltage the state of each comparator above is reported through spi. when L9658 detects one of the above conditions, it set the respective spi status bit to indicate the condition. any of the above conditions will be co nsidered as normal in a high side mos diagnostic. the high side driver is turned off when t timeout is expired. a fault detection filter, t flt_dly , is provided to protect against short-transients on sqh and sql pins. 4.10.9 loss of ground when any of the power grounds (gnd0 ? 7) are lost, no deployment can occur to the respective deployment channels. a loss of gr ound condition on one or several channels will not affect the operation of the remaining channels. when a loss of ground condition occurs, the sour ce of the low side mo s will be floating. in this case, no current will flow through the low side driver. this condition will be detected as a fault by a low side mos diagnostic. also, the resistance measurement result will be on the low end of the resistance range. L9658 functional description doc id 14219 rev 3 31/64 figure 17. high side driver diagnostic flow chart c y n spi command: disconnect i bias y n spi command: hs fet test t timeout = 2ms t flt_dly = 20 s note: spi transmission and spi command can be sent in the same cs_d. turn on hs fet end switch off hs fet disconnect i bias y spi transmission spi command: disconnect i bias y n n (sqh-sql) > v i_th or sql < sg th during t flt_dly y n sqh > sb th during t flt_dly y n set spi.diag.sb th set spi.diag.vith or set spi.diag.sgth t > t timeout clear v i_th , sb th , and sg th bits spi response: send v i_th , sb th and sg th bits sqh < sb th and sql > sg th y n set spi.diag.sb th and set spi.diag.sg th y y n spi command: d6..d4 == d2..d0 set spi.diag.sb th and set spi.diag.sg th and set spi.diag.v i_th n spi command diag mode d11=0 or cmd mode message y n begin sqh > sb th during t flt_dly spi command: connect i bias sql < sg th during t flt_dly clear sbth and sgth bits y spi response: send sbth and sgth bits set spi.diag.sb th set spi.diag.sg th n spi transmission y y clear spi.diag.sg th clear spi.diag.sb th n sqh < sb th during t flt_dly n sql > sg th during t flt_dly y y n functional description L9658 32/64 doc id 14219 rev 3 4.11 deployment driver spi bit definition the spi provides access to read/write to the registers internal to the device, which responses to various deployment driver commands summarized in table below. L9658 response to the previous command is sent in the next valid cs_d. 4.11.1 deployment driver mosi bit definition mosi mode bits are defined as shown in below table. table 13. deployment driver spi response mode bits mosi command mode bits miso response d15 d14 d15 d14 d13 0 0 register mode 0 0 0 register mode 0 1 command mode 0 1 0 command mode 1 0 diagnostic mode 1 0 x diagnostic mode 1 1 monitor mode 1 1 0 status response x x spi transmission fault 1 1 1 spi fault response table 14. mosi bit layout msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 15. mosi mode bits definition bit d15 bit d14 description 0 0 register mode 0 1 command mode 1 0 diagnostic mode 1 1 monitor mode L9658 functional description doc id 14219 rev 3 33/64 4.11.2 deployment driver register mode register mode message are defined here below. odd parity check includes all 16 bits. ?don?t care? bit is included in the parity check as well. when bit d12 is set to ?0,? device ignores bit d11 through bit d0. this is a read request. in the next valid cs_d, a register mode response will contain the pulse stretch timer register. if bit d12 is set to ?1,? bit d11 determines whether the message is intended to program the duration of the pulse stretch timer or to address the soft reset sequence. when bit d11 is set to ?0,? device ignores bit d7 through bit d0. when bit d11 is set to ?1,? bit d9 and bit d8 will be ignored. bit d10 is used to select between two deployment conditions. when bit d10 is set to 0, deployment events on all channels shall have the deployment current of i depl_12a and the deployment period of t depl_2ms . when bit d10 is set to 1, deployment events on all channels shall have the deployment current of i depl_175a and the deployment period of t depl_1ms . the default state of this bit shall be %0. table 16. mosi register mode message definition bit state description d15 0 mode bits d14 0 d13 odd parity d12 0 read (default) 1write d11 0 pulse stretch timer period 1 soft reset sequence d10 0 deployment condition: i deploy_12a and t deploy_2ms 1 deployment condition: i deploy_175a and t deploy_1ms bit state description d9 - pulse stretch timer (see table 17) d8 - d7 - soft reset sequence d6 - d5 - d4 - d3 - d2 - d1 - d0 - functional description L9658 34/64 doc id 14219 rev 3 bit d9 and bit d8 are used to set the period of pulse stretch timer. the device have 8 independent timers. either a valid arming signal or a spi deployment command is able to start the pulse stretch time r. these bits will set th e timer durat ion. these values default to %00 after a por event. bit d7 through bit d0 will be used for a so ft reset sequence. the soft reset for the deployment driver is achieved by writing $aa and $55 within two subsequent 16-bit spi transmissions. if he sequence is broken, the processor will be required to re-transmit the sequence. L9658 does not reset if the sequence is not completed within two subsequent 16-bit spi transmissions. this soft reset function is available only to deployment drivers. when soft reset command is received, the deice reset its deployment driver?s internal logic and timer. the effects of soft reset to the deployment driver is the same as ones of por event, except miso response. during a deployment, soft reset sequence is ignored. 4.11.3 deployment driver command mode command mode message is defined as shown below. table 17. pulse stretch timer bit d9 bit d8 stretch period (ms) 00 7.5 01 15 10 30 11 60 table 18. mosi command mode message definition bit state description d15 0 mode bits d14 1 d13 odd parity d12 - don?t care d11 - don?t care d10 - don?t c are d9 - don?t care d8 - don?t care d7 0 channel 7 idle (default) 1 deploy channel 7 d6 0 channel 6 idle (default) 1 deploy channel 6 L9658 functional description doc id 14219 rev 3 35/64 odd parity check includes all 16 bits. ?don?t care? bit is included in the parity check as well. bit d7 to bit d0 are used to start the deployment or the pulse stretch timer. L9658 provides an independent timer for each channel. when any of these bits are set to ?1,? device starts the deployment or the pulse stretch timer for the respective channels. if any of these bits are set to ?0? when the puls e stretch timer is still active, the pulse stretch timer for the respective channels is terminated. once deployment is initiated, can not be terminated. during a deployment, any commands directed to the channel that are in deployment are ignored. 4.11.4 deployment dri ver diagnostic mode diagnostic mode message are defined as shown here below. d5 0 channel 5 idle (default) 1 deploy channel 5 d4 0 channel 4 idle (default) 1 deploy channel 4 d3 0 channel 3 idle (default) 1 deploy channel 3 d2 0 channel 2 idle (default) 1 deploy channel 2 d1 0 channel 1 idle (default) 1 deploy channel 1 d0 0 channel 0 idle (default) 1 deploy channel 0 table 18. mosi command mode message definition (continued) bit state description table 19. mosi diagnostic mode message definition bit state description d15 1 mode bits d14 0 d13 odd parity d12 0 read diagnostic mode response (default) 1 write diagnostic mode command d11 0 mos diagnostic disable (default) 1 mos diagnostic enable d10 0 ls mos diagnostic enable 1 hs mos diagnostic enable functional description L9658 36/64 doc id 14219 rev 3 odd parity check includes all 16 bits. ?don?t care? bit is included in the parity check as well. when bit d12 is set to ?1,? device executes bit d12 through bit d0. otherwise, bit d12 through bit d0 is ignored. diagnostic mode response is sent in the subsequent spi transmission regardless of bit d12. the diagnostic currents comprise of diagnostic bias current (i bias ) and resistance measurement current (i src ). diagnostic bias current is used to run continuity tests, e.g. short to battery, short to ground, and open circuit tests. during a resistance measurement, i src and i sink is turned on. i src and i sink are turned on when bit d8 is ?1,? bit d9 is ?1,? bit d11 is ?0,? and bit d12 is ?1.? otherwise, i src and i sink are off. when bit d11 is set to ?1,? mos diagnostic is enabled. depending upon the state of bit d10, either a low side mos or a high side mos will be switched on. when bit d 11 is set to ?0,? mos diagnostic is disabled and bit d10 ignored. when bit d9 is set to ?1,? a diagnostic current source is enabled. bit d8 determine if i bias or i src will be switched on. when bit d9 is set to ?0,? the diagnostic curr ent sources is disabled and bit d8 ignored. bit d2 through bit d0 selects a specific channel, which will be connected. the decoding scheme of this channel selection is shown ahead. continuity tests and mos diagnostics are performed through comparators which set proper bits on diagnostic register. differential amplifier used for squib resistanc e measure reflects the scaled voltage across sqh and sql pins. aout is connected to the differential amplifier. externally, aout pin will be connected to an adc input of a processor. w hen bit d7 is set to '1,' aout output is enabled. otherwise, aout is in a high impedance state. multiple devices may be connected to a single adc input of a processor. if an aout is driven, the rest of aout shall be driven to the high-impedance state. d9 0 diagnostic current disable (default) 1 diagnostic current enable d8 0 diagnostic bias current, i bias , enable 1 resistance measurement current, i src , enable d7 0 aout disable (default) 1 aout enable d6 - aout/comparator channel select d5 - d4 - d3 0 aout: resistance measurement (default) 1 aout: calibration d2 - diagnostic current: channel select d1 - d0 - table 19. mosi diagnostic mode message definition (continued) bit state description L9658 functional description doc id 14219 rev 3 37/64 the current sources (ibias and isrc) and the aout/comparators multiplexers are independently selectable. these multiplexers can address the same channel or individual channels. they cannot address multiple channels concurrently. it is not possible to source diagnostic current to more than one channel at a time. the aout multiplexer also selects the measurement channel for the short to ground sgth and short to battery sbth comparators. please see figure 13 for the deployment driver diagnostic block diagram. this flexibility in multiplexer addressing permits the detection of short between loops. to detect a short, enable the diagnostic current, direct it to channel x and monitor the miso diagnostic mode response bit d7 on the other channels. if no short exists between channel x and the channel unde r measurement, the miso diagnos tic mode response will report a sql voltage below sgth threshold (d7=1). if a short exists between channel x and the channel under m easurement, the mosi diagnostic mode response will report a sql voltage above sgth threshold (d7=0). diagnostic of multiple device, requires the abilit y to turn on a current source in one device, while reading aout voltage of another device. use the mosi diagnostic mode message to co nfigure the device and the miso diagnostic mode response to measure the results. ta b l e 1 9 and 20 define the mosi diagnostic mode message and miso diagnostic mode response bits respectively. bit d6 through bit d4 selects a specific channe l, which will be monitored. if aout output is enabled, aout shall reflect the voltage on the selected channel. also, sb th and sg th status bits shall report the status of the respective channel. the decoding scheme of this channel selection is shown in the following table. the default states of these bits are ?0? (channel 0 selected). bit d3 is used to calibrate aout. if this bit is set to ?1,? aout pin contains the calibration voltage. the processor can use this calibration voltage to make adjustment to the subsequent resistance measurement reading. this is intended to improve the accuracy of the resistance measurement. when this bit is set to ?0,? aout pin contains the resistance measurement results. the default state of this bit is ?0.? table 20. channel selection decoding bit d6 bit d5 bit d4 channel selected bit d2 bit d1 bit d0 0000 0011 0102 0113 1004 1015 1106 1117 functional description L9658 38/64 doc id 14219 rev 3 4.11.5 example of short between loops diagnostic the following spi frame sequence is an example how to detect a short between channel 0 and the other channels. the symbol % designates the bit to be tested. this bit is cleared to a 0 when there is a short between the selected channels. bits d13 (short to battery) and d3 (over current on squib) are relevant too. both of them must be at 0 for no fault. it may happens that after leakage test on channel y, channel y is shorted to battery, so when x is biased and y monitored for s horts between channels, d7=d3=0 while d13=1. this will highlight a short to battery. 1. enable the diagnostic current; select ibias current; set the ibias/isrc multiplexer to channel 0; set the aout/comparators mult iplexer to channel 1. the miso read will depend on the previous mosi message. 2. set the aout/comparators mu ltiplexer to channel 2. the miso read will be the results of the channel 0 to channel 1 test. 3. set the aout/comparators mu ltiplexer to channel 3. the miso read will be the results of the channel 0 to channel 2 test. 4. set the aout/comparators mu ltiplexer to channel 4. the miso read will be the results of the channel 0 to channel 3 test. 5. set the aout/comparators mu ltiplexer to channel 5. the miso read will be the results of the channel 0 to channel 4 test. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 1 1 0 01000010000 mosi x x x x x xxxxxxxxxxx d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 1 1 0 01000100000 mosi 1 0 0 0 0 010%0010000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 0 1 0 01000110000 mosi 1 0 0 0 0 010%0100000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 1 1 0 01001000000 mosi 1 0 0 0 0 010%0110000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 0 1 0 01001010000 mosi 1 0 0 0 0 010%1000000 L9658 functional description doc id 14219 rev 3 39/64 6. set the aout/comparators mu ltiplexer to channel 6. the miso read will be the results of the channel 0 to channel 5 test. 7. set the aout/comparators mu ltiplexer to channel 7. the miso read will be the results of the channel 0 to channel 6 test. 8. mosi message will configure the device to test for a short between channel 1 and the remaining channels. previously verified is the integrity of channel 0 to 1. set the ibias/isrc multiplexer to channel 2; set th e aout/comparators multiplexer to channel 3. the miso read will be the results of the channel 0 to channel 7 test. clearing the mosi diagnostic mode message d7 places the aout pin in high impedance. this feature allows the connection of multiple aout pins to a single a/d input. only one aout pin should enabled at any given time. 4.11.6 deployment driver monitor mode monitor mode message is defined as shown in the following table. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 0 1 0 01001100000 mosi 1 0 0 0 0 010%1010000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 1 1 0 01001110000 mosi 1 0 0 0 0 010%1100000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso 1 0 1 1 0 01000100001 mosi 1 0 0 0 0 010%1110000 table 21. mosi monitor mode message definition bit state description d15 1 mode bits d14 1 d13 - odd parity d12 - don?t care d11 - don?t care d10 - don?t care d9 - don?t care d8 0 report deploy success flag (default) 1 report deployment or deploy success flag d7 0 keep deploy success flag channel 7 (default) 1 clear deploy success flag channel 7 functional description L9658 40/64 doc id 14219 rev 3 odd parity check includes all 16 bits. ?don?t care? bit is included in the parity check as well. bit d8 is used to select the meaning of bit d7 through bit d0 in the status response message. when this bit is set to ?1,? bit d7 through d0 in the status response message report the deployment status or the deploy success flag. once the deployment starts, bit d7 through bit d0 report ?1? until the deploy success flag is cleared. bit d7 through bit d0 shall not report ?0? before the deploy success flag is cleared. the default state of this bit is ?0.? when this bit is ?0,? bit d7 through bit d0 in the status response message report the dep loy success flag. deploy success flags are cleared by bit d7 through bit d0 in the monitor mode command. deployment status bits report the deployment state. if the deployment is active during a rising edge of cs_d, deployment status bits is set to ?1.? otherwise, is set to ?0.? if bit d8 in the monitor mode command changes state, bit d7 through bit d0 report the proper states of the internal signals/flags. deploy command success bit indicates if the corresponding channel has finished its deployment sequence. this bit is set when deployment period, tdeploy, has expired. once this bit is set, it will inhibit the subs equent deployme nt command unt il a spi command, to clear this deployment success flag, is received. bit d7 through bit d0 is used to clear/keep the deploy success flag. when these bits are set to ?1,? the flag can be cleared. otherwise, the state of these flags is not affected. d6 0 keep deploy success flag channel 6 (default) 1 clear deploy success flag channel 6 d5 0 keep deploy success flag channel 5 (default) 1 clear deploy success flag channel 5 d4 0 keep deploy success flag channel 4 (default) 1 clear deploy success flag channel 4 d3 0 keep deploy success flag channel 3 (default) 1 clear deploy success flag channel 3 d2 0 keep deploy success flag channel 2 (default) 1 clear deploy success flag channel 2 d1 0 keep deploy success flag channel 1 (default) 1 clear deploy success flag channel 1 d0 0 keep deploy success flag channel 0 (default) 1 clear deploy success flag channel 0 table 21. mosi monitor mode message definition (continued) bit state description L9658 functional description doc id 14219 rev 3 41/64 4.11.7 deployment dri ver miso bit definition miso mode bits are defined as below table. 4.11.8 deployment driver register mode response register mode response is the default response to the processor. after por event, resetb negated, and loss of gnd, the devi ce send $0000 in mi so for the first spi transmission. register mode response is defined as shown in the following table. table 22. miso bit layout msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 23. miso mode bits definition bit d15 bit d14 description 0 0 register mode response 0 1 command mode response 1 0 diagnostic mode response 1 1 status response/spi fault response table 24. miso register mode response definition bit state description d15 0 mode bits d14 0 d13 0 don?t care d12 - echo of mosi read/write bit d11 0 pulse stretch timer duration 1 soft reset sequence d10 0 deployment condition: i deploy_12a and t deploy_2ms 1 deployment condition: i deploy_175a and t deploy_1ms d9 - pulse stretch timer (see ta bl e 1 7 ) d8 - d7 0 don?t care d6 0 don?t care d5 0 don?t care d4 0 don?t care d3 0 don?t care d2 0 don?t care d1 - hard reset status d0 - soft reset sequence status functional description L9658 42/64 doc id 14219 rev 3 bit d12 used to reflect the status of mosi read/write bit. bit d11 used to reflect the mosi bit d11 in the previous command. bit d10 is used to indicate the deployment condition set in L9658. refer to section 5.10.2 for deployment condition bit in mosi register mode message. bit d9 and bit d8 used to report the period of the pulse stretch timer. bit d1 shall be used to indicate a "hard-reset" event. this bit shall be de-asserted ('0'), when por is detected, resetb is asserted, riref is out-of-range, or gnd connection is lost. this bit shall be set to '1,' after the bit has been read. a soft reset sequence shall not affect this bit. bit d0 used to report the soft reset sequence status. if valid soft reset sequences are received, bit d0 is set to ?1.? otherwise, bit d0 is set to ?0.? when L9658 receives valid soft reset sequences, it will send miso register mode response containing $0001 in the next spi transmission. 4.12 miso register mode response summary table 24 below summarizes the miso register mode response of various events and mosi messages. the moiso response shown here is the one received in the next valid spi transmission after each event or mosi write. table 25. miso register mode response summary event/mosi message miso response por $0000 resetb $0000 loss of gnd $0000 r iref out of range $0000 mosi write soft reset: $aa $1x02 mosi write soft reset: $55 (after $aa) $0003 mosi write pulse stretch timer $1x02 L9658 functional description doc id 14219 rev 3 43/64 4.12.1 deployment dri ver command mode response command mode response is defined as shown here after. depen status flag (bit d12) in dicates the state of depen pin. arm status flag (bit d11 through bit d8) indicates the state of the respective arming signal, including the pulse stretch timer. if the pulse stretch timer is initiated by a deployment command, it shall not assert the arming status flag. this flag will be negated as soon as the de-glitch timer is expired. arm status flag is an or-function of arming states from two channels. spi deploy command status flag indicates the spi deployment status for the respective channel. these flags reflects bit d7 through bit d0 of the most recent spi command mode message. these bits do not include the status of pulse stretch timer. these bits will be overwritten by the most rece nt spi command mode message. table 26. miso command mode response definition bit state description d15 0 mode bits d14 1 d13 - don?t care d12 0 depen negated 1 depen asserted d11 0 arm67 negated 1 arm67 asserted d10 0 arm45 negated 1 arm45 asserted d9 0 arm23 negated 1 arm23 asserted d8 0 arm01 negated 1 arm01 asserted d7 - spi deploy command status: channel 7 d6 - spi deploy command status: channel 6 d5 - spi deploy command status: channel 5 d4 - spi deploy command status: channel 4 d3 - spi deploy command status: channel 3 d2 - spi deploy command status: channel 2 d1 - spi deploy command status: channel 1 d0 - spi deploy command status: channel 0 functional description L9658 44/64 doc id 14219 rev 3 4.12.2 deployment driver diagnostic mode response diagnostic mode response is defined as shown in table. sb th threshold status flag (bit d13) indicates the state of sb th comparator. sb th comparator monitors the voltage on sqh pin. depen status flag (bit d12) in dicates the state of depen pin. mos diagnostic status flag (bit d11) report the status of a driver diagnostic. this bit is not latched. when a mos diagnostic has already comp leted, this bit is cleared. low side or high side mos diagnostic status flag (d10) indicates if there is an on-going low or high side driver diagnostic. this bit shall be use in conjunction with bit d11. diagnostic current status flag (d9) indicates the state of diagnostic current. bit d8 indicates which diagnostic current is selected. this bit sh all be used along with bit d9 to indicate if a diagnostic bias current or resistance measurement current is on or off. sg th threshold status flag (bit d7) indicates the state of sg th comparator. sg th comparator monitors the voltage on sql pin. table 27. miso diagnostic mode response definition bit state description d15 1 mode bits d14 0 d13 0 sqh voltage below sb th threshold 1 sqh voltage above sb th threshold d12 0 depen negated 1 depen asserted d11 0 mos diagnostic completed 1 mos diagnostic in-progress d10 0 ls mos diagnostic selected 1 hs mos diagnostic selected d9 0 diagnostic current off 1 diagnostic current on d8 0 diagnostic bias current, i bias selected 1 resistance measurement current, i src selected d7 0 sql voltage above sg th threshold 1 sql voltage below sg th threshold d6 - aout/comparator channel selection d5 - d4 - d3 0 squib current below v i_th threshold 1 squib current above v i_th threshold d2 - diagnostic current: channel selection d1 - d0 - L9658 functional description doc id 14219 rev 3 45/64 aout/comparator channel select bits (bit d6..4) indicate which channel is being monitored by aout or sb th , sg th , v i_th comparators. v i_th threshold status flag (bit d3) indicates the state of v i_th comparator. v i_th comparator monitors the voltage across sqh and sql pins. diagnostic current channel select bits (bit d2..0) indicate which channel is being applied by the diagnostic current. 4.12.3 deployment driver status response status response is defined as in following table. table 28. miso status response definition bit state description d15 1 mode bits d14 1 d13 0 always 0 d12 0 depen negated 1 depen asserted d11 0 arm67 negated 1 arm67 asserted d10 0 arm45 negated 1 arm45 asserted d9 0 arm23 negated 1 arm23 asserted d8 0 arm01 negated 1 arm01 asserted d7 0 no deployment event: channel 7 1 deploy status: channel 7 d6 0 no deployment event: channel 6 1 deploy status: channel 6 d5 0 no deployment event: channel 5 1 deploy status: channel 5 d4 0 no deployment event: channel 4 1 deploy status: channel 4 d3 0 no deployment event: channel 3 1 deploy status: channel 3 d2 0 no deployment event: channel 2 1 deploy status: channel 2 d1 0 no deployment event: channel 1 1 deploy status: channel 1 d0 0 no deployment event: channel 0 1 deploy status: channel 0 functional description L9658 46/64 doc id 14219 rev 3 depen status flag (bit d12) in dicates the state of depen pin. arm status flag indicates the state of the respective arming signal, including the pulse stretch timer. if the pulse stretch timer is initiated by a deployment command, it does not assert the arming status flag. this flag is de/asserted as soon as the de-glitch timer is expired. deploy status bits (bit d7 through bit d0) report the status of internal deployment. bit d8 in the monitor mode command determines which status information device needs to be reported in d7 through bit d0. 4.12.4 deployment dr iver spi fault response this spi fault response indicates a fault in the last mosi transmission. the device uses the parity bit to determine the integrity of the mosi command transmission. this response is defined as shown in the following table. 4.13 arming spi bit definition 4.13.1 arming mosi_a bit definition arming mosi_a is defined as shown in figure below. 4.13.2 arm[01..67] arming command. these bits are used to en able/disable arming signal. a value of 1 enables the arming signal for the respective loop-pair. a value of 0 disables the arming signal for the respective loop-pair. when device is in reset, all arming signals are disabled. table 29. miso spi fault response bit state description d15 1 always ?1? d14 1 always ?1? d13 1 always ?1? d12 0 parity error or message error during a deployment (1) 1. when a parity error is detected, the L9658 reports e000h. during a deployment, when an invalid message is detected, he L9658 reports also e000h. refer to table 12 for the description of an invalid message during a deployment. bit d12 reports an incorrect number of cloc ks/bits. when an incorrect number of clocks/bits is detected, bit d12 is asserted (f000h). 1 incorrect number of clocks/bits d11 ? d0 0 don?t care table 30. arming mosi _a bit definition 7654321 0 arm67 arm45 arm23 arm01 ar m67* arm45* arm23* arm01* L9658 functional description doc id 14219 rev 3 47/64 4.13.3 arm[01..67]* arming-command complement. these bits are the complements of arm[01..67] bits and will be used to confirm the transmission of ar ming signals. if L9658 does not receive valid complement bits, it will ignore the arming command. 4.13.4 arming miso_a bit definition arming miso_a is defined in table below. 4.13.5 arm[01..67] arming status. these bits are used to echo arming bits sent in the previous arming command. a value of 1 indicates that arming signal is enabled for the respective loop-pair. a value of 0 indicates that arming signal is disabled for the respective loop-pair. the default state of these arming signals is ?0? (disabled). 4.14 satellite sensor interface the device provide four currents limited to 60ma each through outputs ich1, ich2, ich3 and ich4. the voltage at these four channels is supplied by the v8buck input. channels 1, 2, 3 and 4 serves as switched power sources to remote mounted sate llite sensors, each will draw 2 current levels. the L9658 will monitor the current flow from its output pin and ?demodulate? the curr ent to be decoded using manche ster protocol. decoded satellite message is communicated to an external microprocessor via spi. figure 18. satellite interface block diagram table 31. arming miso _a bit definition 7654321 0 arm67 arm45 arm23 arm01 arm67 arm45 arm23 arm01 msg current sense with stb blocking fet current limit (stg protect) fifo spi in spi out control configurati on register ccrx /mcr manchester decode & crc or parity check ichx v8buck satellite status bits functional description L9658 48/64 doc id 14219 rev 3 4.14.1 current sensor each output channel senses the current draw n by the remote satellite sensor; the circuit modulates the load current into logic voltage levels for post processing by a manchester decoder. each channel has an internal comparator with a programmable currents trip points selectable through the appropri ate setting in the ccr regist er for each of the 4 satellite channels. the current sense comparator provides a hysteresis, which can be enabled through appropriate setting in the ccr register. each comparator output have a de-glitch filter as a function of the protocol speed as defined in the ac characteristic table. each current is limited to 150 ma maximum and includes a fault timer. if the output for a given channel is in current limited for a period of time exceeding the output fault timer, the ic will report an over current fault via spi and latch off the affected channel, the channel will remain in latch off mode until the user send a spi command to re-activate the channel. when the output is shorted to battery, an internal comparator senses the output voltage level then turn off an internal series transistor to provide blocking diode for the current goin g through the output channe l, the output will resume normal operation once the fault condition is removed. the comparator have 20 to 50 mv input offset to prevent turning off the output und er an open circuit cond ition. in case of lo ss of vcc all output will remain off. 4.14.2 manchester decoding the L9658 decodes satellite mass ages based on manchester de coding, each of the four satellite channels have a manche ster decoder that can be enabled or di sabled through the ccr register. an example of manchester decoding is given below; logic 0 is defined as a signal transition from 0 to 1 at 50 % duty cycle, logic 1 is defined as a signal transition from 1 to 0 at 50 % duty cycle. the ic starts decoding the satellite message afte r it receives two sync bits defined as logic 00, the sync bits are used to determine the bit rate of the incoming message and are used as the time base in decoding the following bits; different bit rates ranges are programmable via spi, in case the measured bit rate obtained using the 2 sync bits doesn?t fall within the range selected by he spi as defined, the device declares a bit time error, revert to the minimum bit time of the selected range, and wait for idle. figure 19. manchester decoding 1 010 010 id le L9658 functional description doc id 14219 rev 3 49/64 figure 20. manchester decoding using satellite protocol as an example the decoder uses a counter to track the high to low and low to high transitions at the bit center. a transition is considered a bit center only when an edge is detected 75 % to 125 % of the reference bit time. when a single edge occurs below 75% of the reference bit time it is considered to be a bit edge but it is ignored. when the decoder detects a second edge below 75 % of the reference bit time the device declares a bit time error via spi, revert to the minimum bit time of the selected range, and wait for idle. when a valid bit center is detected the counter will reset and start co unting again until an other edge is detect ed. if the message is not complete and no edge is detected in the range of 75 % to 125 % of measured bit time, the device declares a bit time error via spi, revert to the minimum bit time of the selected range, and wait for idle. the idle time is defined as 150 % of the minimum bit time of the selected protocol speed range. if there is no bit transition detected for that period of time and the correct number of bits was received, the message is considered complete. bit time error and too many bits faults are stored directly into the fifo once they are selected without the need to wait till an idle time. since a bit time error is reported directly once it is detected before idle time, too few bits error may never be reported since bit time error is detected first. bit time errors and too many bits errors will c ause the decoder to revert to the minimum bit time of the selected range, and discard the message. in case of a message containing multiple errors only one error code is reported per message, errors detected in the decoding phase have the following reporting priority; bit time errors, too many bits errors then communication errors (crc/parity). 0 23 4 18 1 19 0 bit_time_counter functional description L9658 50/64 doc id 14219 rev 3 upon power up or after a reset, the device requires at least 1.5 idle bit-time based on 52.33khz protocol speed or 28.65us before star ting to decode the first message, bit-time shall adapt to the period obtained based on the two sync bits there after. 4.14.3 communication protocols the L9658 supports two different communication protocols that are widely used by different automotive manufactures. one is based on the protocol used by "a" satellite sensors and the other is "b" protocol that supports variable length messages based on bosh, pas3 and pas4 protocols. bits d11d12 in the ccr register are used to configure the device in order to use any of these protocols. 4.14.4 "a" protocol the delphi sensors satellites protocol supported by this device is shown below. the message consists of 5 bits crc cyclic redundancy check error, 12 bit of data and two sync bits. this information could be sensor?s trace-ab ility data, or crash severity or velocity data. the two most significant bits in the data field sent by the sensor can identify these data types. figure 21. "a" satellite protocol the crc error detection code is based on the polynomial x 5 + x 2 + 1. the L9658 processes all incoming message through the crc verificati on and report an erro r message via spi in case of a crc mismatch. crc is performed after a complete message is received, and in case of crc error, he device sets a fault code via spi. 4.14.5 "b" variable length protocol figure 22. "b" satellite protocol the L9658 ic shall supports "b" satellite protocol, which is based on bosch sensors pas3\pas4 protocols (in figure 22 bit order is opposite to pas3/pas4 protocol in which lsb is sent first and msb last) with added flexibility that the mess age length in the data field can be programmed to accept any number of bits between 8 and 11. the protocol consists of a parity bit, a data field (configurable between 8 to 11 bits) and two sync bits. the ic can be enabled to use this protocol through the appropriate setting in the mcr register. once the protocol is enabled for a specific channel, the protocol speed is configured by setting the appropriate bits in the ccr register for that particular channel. a parity check is performed after a complete message is received, and in case of a parity error, the device sets a fault code via spi. data crc 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 sync1 idle msb lsb sync2 18 idle2 idle1 data 5 6 7 8 9 10 11 12 13 0 1 2 3 4 sync1 idle lsb sync2 idle2 idle1 msb L9658 functional description doc id 14219 rev 3 51/64 4.14.6 fifo buffer the ic includes 4 internal fifo buffers; one fo r each output channel, each one is 12 bits and two levels deep. when d1 in the mcr register is set to 0 (default condition), msg pin is asserted and remain asserted as long as there is a message in any of the 4 internal fifo buffers. the fifo provides error flag via spi in case of buffer data loss. when writing to a full fifo the old data is lost. for example if the fifo content at the bottom of the stack is $0aa, an incoming message of $090 will o ccupy the upper level of the fi fo stack, at this stage the fifo is full, but the data lost flag is not set. when writing another message to the fifo, for example $066, the data lost flag is set and the final fifo content is $066 (top of stack) and $090(bottom of stack). when a fifo read operation is performed via spi, the fifo content $090 is carried over by miso and data lost flag is unset. the data lost flag is also unset when the fifo is flushed via spi command. 4.14.7 satellite continuity check each output has a short circuit protection by independent current limit. when a short circuit occurs the output becomes current limited, a fault timer latch the output off and a fault condition bit is reported via spi. that output returns to normal operation when it is re-enabled via spi and the current limit condition was removed, this fault condition does not interfere with the operation of any of the other output channels 4.14.8 (ifx/vx) hall effect support mode channels 3 and 4 of the L9658 can by used to provide an analog feed back current as a 1/100th ratio of the sense current in this mode internal fifo and decoder are bypassed. this will allow the if3/v3 and if4/v4 pins to be connected to a re sistor to ground and provide an analog voltage equivalent to the sense current to be read by an a/d port. these two pins have an internal clamp as protection. this mode of operation is accessed by the setting of d4 and d5 in the mcr register. when d4 and d5 are set to 1, pins if3/v3 and if4v4 is configured as analog current output with 1/100th ratio of the sense current. this feature is available for channels 3 and 4. 4.14.9 (ifx/vx) raw data out mode when d4 and d5 in the mcr register are set to 0 the if3/v3 and if4/v4 pins are configured as discrete output pins that provide logic level output voltage of the sensed current based on the internal current th reshold set by the user through th e ccr register, which when used in conjunction with satellite sensors connected to channel s 3 and 4 it can provide raw data out of the satellite message bypa ssing the internal decoder. the output voltage has a reversed polarity to the satellite current such that when the current drawn by the satellite is below the current de tection threshold, the ifx/vx signal level transitions into a high state, on the other hand if the current drawn by the satellite exceed the current detection threshold, ifx/vx signal transitions into a low state. bits d6 and d7 in the mcr register is used to disable this output if it is not used. functional description L9658 52/64 doc id 14219 rev 3 4.14.10 message waiting the msg pin is asserted when there is a message in any of the 4 internal fifo buffers. this pin is ttl level and is configurable to be either active high or active low signal. the pin shall also be programmable via spi to either remain active during cs_s once is set or inactive during cs. if the pin is configured to remain active during cs_s and there is a message in any of the internal fifo it remains active even if cs_s is de-asserted. however if there are no mess ages in any of the internal 4 fifo s the pin will be forced to inactive state. 4.14.11 satellite serial data input (mosi) the mosi input takes data from the master microprocessor while cs_s is asserted. the msb is the first bit of each word received on mosi and the lsb is the last bit of each word received on mosi. this pin has ttl level co mpatible input volta ges allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. mosi bits layout is provided here below. 4.14.12 satellite mosi bits definition there are total of 5 inte rnal registers that are used to configure all of the satellite channels. these registers are addressed by setting mosi bit 14 according to this table and by sending the spi commands sequentially in the correct order such that ch1 command is the first significant word and ch4 command is the last word. the spi command sequence is such that the first word communicates with channel 1, the second spi word communicates with channel 2, the third spi word is in communication with channel 3 and the 4th word with channel 4. table 32. satellite mosi bits layout 1514131211109876543210 p s data (12:0) table 33. mosi satellite interface registers map bit state description d15 spi odd parity d14 0 mcr master configuration register (ch1 only) 1 ccr1 channel configuration register for ch1 1 ccr2 channel configuration register for ch2 1 ccr3 channel configuration register for ch3 1 ccr4 channel configuration register for ch4 L9658 functional description doc id 14219 rev 3 53/64 4.14.13 satellite module confi guration register (ch1 only) this register define global configuration to the satellite module, in able to be executed correctly it has to be written for ch1 as the first word after the rising edge of cs_s. when an mcr command is written to any other channel than ch1, the ic ignores this command and reply with spi message $e000. bits[1:0] these bits configure the polarity and the behavior of the msg bits[7:4] these bits are used to enable ch3 and ch4 to operate in hall effect sensor mode, disabled by default table 34. master configuration register definition (ch1 only) bit state description d13 0 not used - d12 0 "b" protocol setup for even parity (default) 1 "b" protocol setup for odd parity - d11 0 ch4 "a" protocol mode (default) 1 ch4 "b" protocol mode - d10 0 ch3 "a" protocol mode (default) 1 ch3 "b" protocol mode - d9 0 ch2 "a" protocol mode (default) 1 ch2 "b" protocol mode - d8 0 ch1 "a" protocol mode (default) 1 ch1 "b" protocol mode - d7 0 disable if4/v4 pin - 1 enable if4/v4 pin - d6 0 disable if3/v3 pin - 1 enable if3/v3 pin - d5 0 if4/v4 operating in satellite sensor mode (default) 1 if4/v4 operating in hall effect sensor mode - d4 0 if4/v3 operating in satellite sensor mode (default) 1 if4/v3 operating in hall effect sensor mode - d3 0 not used - d2 0 not used - d1 0 msg output remains active when cs_s asserted (default) - 1 msg output inactive when cs_s asserted - d0 0 msg output active high (default) 1 msg output active low - functional description L9658 54/64 doc id 14219 rev 3 bits[11:8] these bits are used configure the output channels for either sensor protocols. in the ?b? protocol mode a parity bit is used to verify communication between th e satellite sensors and the ic. the L9658 calculates the parity of the incoming massage based on either odd parity or even parity, which is determined by the setting of bit d12. in case of communication parity mismatch a communication parity error shall be reported via spi. if none of the channels is configured for the ?b? protocol a write operation to this bit is ignored. bit [12] this bit controls the parity ca lculation for incoming sensor messages to either even or odd parity; the selected setting apply to all channels operating in ?b? protocol node. the setting of this bit is ignored by the ic for the channels configured for ?a? protocol. the mcr register have to written at least once in order for the device to be configured correctly, however it can be superseded with a ccr command. 4.14.14 channel configur ation registers (ccr1, ccr2, ccr3, ccr4) this register is used to conf igure individual cha nnels for proper satellite communication as required by the application please refer to below table 33 for bits definition. table 35. channel configuration register definition bit state description d13 0 don?t flush fifo (default) 1 flush fifo d12 0 write to bits L9658 functional description doc id 14219 rev 3 55/64 bits[2:0] these bits program the threshold for the current demodulation affecting each individual channel. the current ranges supported are given in ta bl e 3 6 . . all incoming satellite signals ar e processed through deglitch filter before reaching the decoder. d3 enables a hysteresis around the current threshold for added noise immunity. bits[5:4] these bits are used to enable the satellite channels and the inter nal decoders to be commanded on or off according to following table. suggested sequence to avoid spurious error code inside fifo is to switch on the channel first, and enable decoder only once satellite is powered. bits[7:6] these bits are used to configure the number of bits in the "b" protocol data field. for these bits to execute on any given channel, the chan nel has to be configured for "b" protocol through bits <11:8> in the mcr register. d2 - current trip point threshold (refer to ta b l e 3 6 ) d1 - d0 - table 36. current ranges supported are given in following table bit d2 bit d1 bit d0 current threshold (ma) 0 0 0 16.50(default) 0 0 1 19.00 0 1 0 22.50 0 1 1 26.50 1 0 0 32.00 1 0 1 39.00 1 1 0 48.50 1 1 1 60.00 table 37. satellite/decoder control bit d5 bit d4 definition satellite decoder 0 0 off (default) off (default) 01onoff 1 0 on on 11offoff table 35. channel configuration register definition bit state description functional description L9658 56/64 doc id 14219 rev 3 bits[9:8] these bits shall configure speed selection for any of the sate llite channels and they apply to both ?a? and the "b" manchester protocol. upon power up or reset the protocol configuration shall initialize to the default sp eed as in shown in below table. bits[11:10] these bits will be used to deter mine the requested informatio n from each of the satellite channels internal registers. at power up or incase of por condition these bits are initialized to 00 by the ic and miso bits <12:0> shall default to the content of the mcr register. table 38. "b" protocol configuration bit d7 bit d6 protocol data field 0 0 8bits(default) 019bits 1 0 10bits 1 1 11bits table 39. bit time selection bit d9 bit d8 guaranteed frequency operating range (hz) 0 0 13.3k to 52.33k (default) 0 1 26.32k to 110.74k 1 0 43.50k to 164.20k 1 1 62.66k to 250k table 40. mode select bit d11 bit d10 definition 00/01/10 report this on next miso bit 13 = spi odd parity bits<15:14 ? 11 (configuration reports mode) 00 if the previous command is a write to the mcr register (default) report <12:0> ta b l e 3 5 (mcr) only for ch1 if previous command is a write to the ccrx register report <12:0> ta b l e 3 6 (ccr) 0 1 report <12:0> ta b l e 3 5 (mcr) (ch1 only) 1 0 report <12:0> ta b l e 3 6 (ccr) 11 report this on next miso bit 13 = spi odd parity bits<15:14 ? (satellite status 00,01 or 10) 1 1 report fifo data L9658 functional description doc id 14219 rev 3 57/64 in the auto reply mode where d11 d10 are set to 00,the ic will test every incoming mosi command, if the command is a write command to a ccrx register then during the following cs_s the device reports back the content of the respective ccrx channel register. if the incoming command is a write to the mcr regi ster for ch1 then in the following cs_s the device reports back the content of the mcr register. if the mosi command is a write to the ccrx register with bits <11:10> are set to 11 the ic reports the content of the fifo. miso bits layout when reporting fifo data is provided, the miso layout when reporting configuration report is provided in previous figure. when reporting a configuration report for either the mcr or the ccr register mosi bits<15:14> are set to 11 to indicate a configuration r eport. otherwise they will report the status of the satellite channel. in some cases the user may request a configuration report for either the mcr or ccrx registers without first performing the write operation mentioned above. in this condition if bits <11:10> are set to 01 by the user, device reports the content of the mcr register on the subsequent chip select. if bits <11:10> are set to 10 the ic reports the content of the ccr register. in case of an spi command to ch2, ch3 or ch4 with bits d11d10 are set to 00 while d14 is set to 0, or if d11d10 are set to 01 with d14 is set to either 0 or 1, the affected channel reports $e000. bit[12] this bit is used to control the write operation for the ccr register. when it is set to 0 the user can modify bits functional description L9658 58/64 doc id 14219 rev 3 4.14.15 spi miso bits lay out for configuration report status bits <15:14> indicate the status ofL9658 output channels, status bits are updated at the falling edge of cs_s and defined by bits <15:14>. fault codes are pushed into the and then removed form fifo on rising edge of cs_s and reported through miso. global and channels faults are encoded in the hexadecimal range between $001 to $01f. ?global faults? covers all satellite channels. ?ch annel fault? covers only a particular channel. channel fault codes are pushed into the fifo onc e each time they occur while global faults are pushed into the fifo once even if the fault is still present. bit 13 is set by the ic to satisfy an odd parity for each of the transmitted word, therefore it will be set to 1 if the total number of 1?s for bits is even and to 0 if the total number of 1?s for bits is odd. table 43. spi miso bits layout when reporting fifo data 1514131211109876543210 m1 m0 p configuration report table 44. miso manchester message data definition bit state description d15 - status bits (refer to ta b l e 4 5 ) d14 - d13 - odd parity d12 0 no fifo data has been lost 1 fifo data has been lost d11:0 fifo contents table 45. status bits definition bit d15 bit d14 definition 0 0 current channel is off 0 1 channel on, message processing disabled 1 0 channel on, message processing enabled 1 1 configuration report table 46. satellites fault codes definition supporti ng ?a? protocol bit d11:0 value fault definition function $0 no faults (fifo empty value) global fault codes definition (reported back for ch1 only & latched only once) $1 unassigned $2 bad mosi bit count $3 - $f unassigned L9658 functional description doc id 14219 rev 3 59/64 buffer data values from $0 to $1f are reserved and not transmitted by the "a" manchester data sensor. all "a" satellite sensors use valu es between $020 and $ fff, therefore values falls within this range will be interpreted by system softwar e as satellite only data. if a satellite data is found to be in the range betw een $00 to $01f the ic asserts the reserved message error flag or fault code. in case there is no fault condition present, the device returns $000. data is lost when a data word is written to a full buffer. to alarm the user for this condition the dl (buffer data lost) flag shall be set. $10 high side current limit exceeded channel fault codes $11 unassigned $12 spi odd parity communication error $13 - $17 unassigned $18 reserved message received $19 manchester bit time error or too few bits $1a too many bits (no idle condition after 19 th bit) $1b reserved $1c crc error $1d - $1f unassigned $020 - $fff manchester sensor ?s data range manchester data table 46. satellites fault codes definition supporti ng ?a? protocol bit d11:0 value fault definition function functional description L9658 60/64 doc id 14219 rev 3 as mentioned earlier the L9658 supports a "b" manchester data protocol, the data field for this protocol can be configured to any number of bits between 8 to 11 bits. incoming data from the sensor using a "b" protocol shall be right justified by the ic. for example if the incoming message has only 8bits in the data filed. the device will transmit this message on miso such that it occupies bits <7:0> bits 8,9 and 10 are set to 000. unlike delphi protocol, lsb will be the first bit on miso. too many bits and too few bits faults can be calculated based on the number of bits in the data field. so if we consider the 8 bit "b" protocol example discussed above a message with 9 bits in the data field should set the too many bits fault flag, on the other hand a message with 7 bits in the data field should set the too few bits fault flag. when the L9658 is configured to use a the manchester "b" protocol, the device set spi mosi d11 to 0 when reporting fault data and to 1 when r eporting satellite data. this operation should allow both sensors "a" based or generic based to use the same fault codes. table 47. satellites fault codes definition supporti ng ?b? protocol bit d11:0 value fault definition function $0 no faults (fifo empty value) global fault codes definition (reported back for ch1 only & latched only once) $1 unassigned $2 bad mosi bit count $3 - $f unassigned $10 high side current limit exceeded channel fault codes $11 unassigned $12 spi odd parity communication error $13 - $17 unassigned $18 unassigned $19 manchester bit time error or too few bits $1a too many bits $1b reserved $1c satellite communication parity error $800 - $fff manchester sensor?s data range d11 shall be set to 1 by the ic when receiving sensor data. when reporting faults d11 shall be set internally by the ic to 0 manchester data table 48. hall effect fault codes definition (ch3 and ch4) only bit d11:0 value fault definition function $0 no faults (fifo empty value) no faults $1 - $f unassigned fault codes $010 high side current limit exceeded $12 spi odd parity communication error L9658 functional description doc id 14219 rev 3 61/64 when either ch3 or ch4 is configured to interface with hall-effect sensor, miso data reported via spi for that specific channel will be as outlined in proper table. global faults are not reported for channels configured in hall effect sensor mode since they are only reported for ch1 while hall effe ct sensor configuration is on ly possible for ch3 and ch4. upon power on or after a rese t or por conditions the miso data will be initialized as follows; ch1 returns mcr configuration in report mode with parity bit is set accordingly. ch2, ch3, and ch4 return $e000 package information L9658 62/64 doc id 14219 rev 3 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. figure 23. lqfp64 mechanical data and package dimensions outline and mechanical data a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.08mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.20 0.0066 0.0086 0.0106 0.0079 c 0.09 0.0035 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 7.50 0.295 e 0.50 0.0197 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 7.50 0.295 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0? (min.), 3.5? (min.), 7?(max.) ccc 0.080 0.0031 lqfp64 (10 x 10 x 1.4mm) 0051434 f ccc L9658 revision history doc id 14219 rev 3 63/64 6 revision history table 49. document revision history date revision changes 28-nov-2007 1 initial release. 10-dec-2010 2 document status prom oted from preliminary data to datasheet. add section 4.11.5: example of sh ort between loops diagnostic on page 38 . 20-sep-2013 3 updated disclaimer L9658 64/64 doc id 14219 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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